AD4022BCPZ-R2

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs AD4020/AD4021/AD4022 Data Sheet FEATURES GENERAL DESCRIPTION Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows...
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Технические характеристики

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Корпус VSON-10
Разрядность АЦП
Кол-во измерительных каналов
Частота захвата сигнала
Тип аналого-цифрового преобразователя
Цифровой интерфейс
Конфигурация аналогового входа
Уровень сигнал/шум
Диапазон питающих напряжений аналоговой части
Диапазон питающих напряжений цифровой части
Диапазон рабочих температур
Примечание ADC, Successive Approximation, 20-Bit, 1 Func, 1 Channel, Serial Access, PDSO10
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20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs AD4020/AD4021/AD4022 Data Sheet FEATURES GENERAL DESCRIPTION Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit, no missing codes SNR: 100.5 dB at fIN = 1 kHz, VREF = 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 µW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C The AD4020/AD4021/AD4022 are high accuracy, high speed, low power, 20-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4020/AD4021/AD4022 power scales linearly with throughput. APPLICATIONS Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems 12 1.8V VDD VIO 1.8V TO 5V IN+ VREF IN– 20-BIT SAR ADC VREF/2 SERIAL INTERFACE STATUS BITS SPAN CLAMP COMPRESSION 0 GND SDO CNV 6 3 0 –3 –6 –9 SDI SCK 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 15369-001 0 TURBO MODE 9 –12 –15 –5 –3 –1 1 3 INPUT DIFFERENTIAL VOLTAGE (V) 5 15369-147 REF HIGH-Z MODE VREF/2 25°C HIGH-Z DISABLED, 1.8MSPS 25°C HIGH-Z ENABLED, 1.8MSPS 15 AD4020/AD4021/AD4022 VREF Fast device throughput up to 1.8 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input/output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply. INPUT CURRENT (µA) 10µF Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin, and eliminating the need for external protection diodes. 18 FUNCTIONAL BLOCK DIAGRAM 2.5V TO 5V Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2). Figure 2. Input Current vs. Input Differential Voltage Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017–2021 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com PDF
Документация на семейство AD4020/AD4021/AD4022 

AD4020/AD4021/AD4022 (Rev. C) 20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs

Дата модификации: 14.02.2022

Размер: 912.3 Кб

40 стр.

20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs AD4020/AD4021/AD4022 Data Sheet FEATURES GENERAL DESCRIPTION Easy Drive Greatly reduced input kickback Input current reduced to 0.5 μA/MSPS Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS First conversion accurate, no latency or pipeline delay Input span compression for single-supply operation Fast conversion allows low SPI clock rates Input overvoltage clamp protection sinks up to 50 mA SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface High performance Differential analog input range: ±VREF, VREF from 2.4 V to 5.1 V Throughput: 1.8 MSPS/1 MSPS/500 kSPS options INL: ±3.1 ppm maximum Guaranteed 20-bit no missing codes SNR: 100.5 dB at fIN = 1 kHz at VREF 5 V THD: −123 dB at fIN = 1 kHz, −100 dB at fIN = 100 kHz SINAD: 89 dB at fIN = 900 kHz (see Figure 17) Oversampled dynamic range 104 dB for OSR = 2 131 dB for OSR = 1024 Low power Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface 2.7 mW at 500 kSPS (VDD only) 83 μW at 10 kSPS, 15 mW at 1.8 MSPS (total power) 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP Pin compatible with AD4003/AD4007/AD4011 family Guaranteed operation: −40°C to +125°C The AD4020/AD4021/AD4022 are high accuracy, high speed, low power, 20-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4020/AD4021/AD4022 power scales linearly with throughput. APPLICATIONS Automatic test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems 12 1.8V VDD TURBO MODE IN+ 20-BIT SAR ADC VREF VREF/2 0 IN– CLAMP SERIAL INTERFACE STATUS BITS SPAN COMPRESSION GND SDO CNV 3 0 –3 –6 –12 SDI SCK 6 –9 VIO 1.8V TO 5V 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 15369-001 0 9 –15 –5 –3 –1 1 3 INPUT DIFFERENTIAL VOLTAGE (V) 5 15369-147 REF HIGH-Z MODE VREF/2 25°C HIGH-Z DISABLED, 1.8MSPS 25°C HIGH-Z ENABLED, 1.8MSPS 15 AD4020/AD4021/AD4022 VREF Fast device throughput up to 1.8 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input/output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply. INPUT CURRENT (µA) 10µF Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin, and eliminating the need for external protection diodes. 18 FUNCTIONAL BLOCK DIAGRAM 2.5V TO 5V Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2). Figure 2. Input Current vs. Input Differential Voltage Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com PDF
Документация на AD4021BCPZ-R2 

AD4020/AD4021/AD4022 (Rev. B) 20-Bit, 1.8 MSPS/1 MSPS/500 kSPS, Easy Drive, Differential SAR ADCs

Дата модификации: 21.11.2019

Размер: 1.02 Мб

39 стр.

    Публикации 1

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