Серия логических ИС CJ74HC138

Общие характеристики

	Раздел	Логическая ИС
	Корпус	SOP-16
	Тип логики
	Логическая функция
	Особенности: High Speed CMOS Logic 3-to-8 Line Decoder/Demultiplexer Inverting and Non-Inverting

Документация на серию CJ74HC138

JIANGSU CHANGJING ELECTRONICS TECHNOLOGY CO., LTD. 3-to-8 Line Decoder/Demultiplexer; Inverting CJ74HC/HCT138 Logic 1 Introduction 3 Features The CJ74HC/HCT138 decodes three binary weighted address inputs(A0, A1 and A2) to eight mutually exclusive outputs (/Y0 to /Y7). The device features three enable inputs (/E1, /E2 and E3). Every output will be HIGH unless/E1 and /E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32(5 to 32 lines) decoder with just four CJ74HC/HCT138 ICs and one inverter. The CJ74HC/HCT138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. • Input levels: - For CJ74HC138: CMOS level - For CJ74HCT138: TTL level • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Active LOW mutually exclusive outputs • Specified from -40°C to +125°C 4 Applications 2 Available Packages PART NUMBER CJ74HC138 CJ74HCT138 PACKAGE • LED Displays • Servers • White Goods • Power Infrastructure • Building Automation • Factory Automation SOP16 Y7 A2 TSSOP16 SOP16 Y6 A1 TSSOP16 Y5 Note: For all available packages, please refer to the part Orderable Information. A0 Y4 E1 Y3 E2 Y2 E3 Y1 Y0 Function block diagram www.jscj-elec.com 1 Rev. – 1.0  PDF

Документация на серию CJ74HC138 

Дата модификации: 14.11.2025

Размер: 326.8 Кб

18 стр.

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