BL1040

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14-Bit, 65 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) BL1040 ◼ Sampling rate to 65 MSPS ◼ SNR = 76.5dBFS @ 10MHz and 65MSPS SFDR = 88dBc @ 10MHz and 65MSPS ◼ IF sampling frequencies to 300MHz ◼ Single 1.8 V analog supply operation Single 1.8 V digital supply operation FUNCTIONAL BLOCK DIAGRAM AVDD VIN+A VIN-A VREF ◼ Parallel CMOS or LVDS output interface SENSE ◼ Low power...
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Внешний вид BL1040

Технические характеристики

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Корпус QFN-64
Разрядность АЦП
Кол-во измерительных каналов
Частота преобразования
Тип аналого-цифрового преобразователя
Цифровой интерфейс
Уровень сигнал/шум
Потребляемая мощность
Примечание 14-Bit, 65 MSPS, 1.8 V Dual Analog-to-Digital Converter
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14-Bit, 65 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) BL1040 ◼ Sampling rate to 65 MSPS ◼ SNR = 76.5dBFS @ 10MHz and 65MSPS SFDR = 88dBc @ 10MHz and 65MSPS ◼ IF sampling frequencies to 300MHz ◼ Single 1.8 V analog supply operation Single 1.8 V digital supply operation FUNCTIONAL BLOCK DIAGRAM AVDD VIN+A VIN-A VREF ◼ Parallel CMOS or LVDS output interface SENSE ◼ Low power: 441mW (65 MSPS) RBIAS ◼ Integer 1-to-8 input clock divider ◼ Integrated ADC sample-and-hold inputs ◼ Multi-chip synchronization function ◼ Programmable internal ADC voltage reference ◼ Flexible analog input range: 1 V p-p to 2 V p-p ◼ Energy-saving power-down modes ◼ Greater than 90 dB channel isolation/crosstalk ◼ Serial port control APPLICATIONS VCM VIN-B VIN+B AGND 14-BIT PIPELINED ADC CORE BIAS & REFERENCE FEATURES 16-BIT PIPELINED ADC CORE DRVDD CMOS/LVDS OUTPUT BUFFER CORRECTION LOGIC DCS & DIVIDE 1~8 CMOS/LVDS OUTPUT BUFFER CORRECTION LOGIC SDIO/ DCS SCLK/ DFS CSB OEB NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 5 FOR LVDS PIN NAMES. Figure 1 ◼ Communications ◼ Mobile phone base station ◼ General-purpose software radios ◼ Broadband data applications ◼ Ultrasound equipment D0A DCOA CLK+ CLOCK GEN SPI PDWN ORA D13A GENERAL DESCRIPTION The BL1040 is a dual, 14-bit, 65 MSPS analog-to-digital converter (ADC). The BL1040 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Flexible power-down options allow significant power savings, when desired. The ADC is powered by a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The BL1040 is available in 64-lead QFN. It is specified over the industrial temperature range of −55°C to +125°C. CLKSYNC ORB D13B D0B DCOB PDF
Документация на BL1040 

Дата модификации: 11.06.2024

Размер: 1.13 Мб

30 стр.

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