BL24C16A-PARC

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BL24C02A/04A/08A/16A Features   Compatible with all I2C bidirectional data – Page Write within 3 ms transfer protocol – Partial Page Writes Allowed Memory array: 2K bits (256X 8) / 4K bits (512 X 8) / 8K –  Write Protect Pin for Hardware Data Protection  Schmitt Trigger, Filtered Inputs for Noise bits (1024 X 8) / 16K bits (2048 X 8) of Suppression EEPROM Page size: 16 bytes –   Single supply voltage and high speed: – 1 MHz  Random and sequential Read modes  – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Enhanced ESD/Latch-up protection HBM 8000V – Write: – High-reliability  Byte Write within 3 ms 8-lead PDIP/SOP/TSSOP/UDFN and WLCSP4 packages Description  The BL24C02A/BL24C04A/BL24C08A/BL24C16A  The device is optimized for use in many provides 2048/4096/8192/16384 bits of serial industrial and commercial applications where electrically erasable and programmable read- low-power only memory (EEPROM), organized as essential. and low-voltage operation are 256/512/1024/2048 words of 8 bits each. Pin Configuration 8-lead PDIP 8-lead SOP 8-lead TSSOP 8-pad DFN WLCSP4 1 A0 1 5 VCC A0 1 5 VCC A0 1 5 VCC VCC 1 5 A0 A1 2 6 WP A1 2 6 WP A1 2 6 WP WP 2 6 A1 A2 3 7 SCL A2 3 7 SCL A2 3 7 SCL SCL 3 7 A2 GND 4 8 SDA GND 4 8 SDA GND 4 8 SDA SDA 4 8 GND Bottem view BL24C02A/04A/08A/16A Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited © 2016 Belling All Rights Reserved www.belling.com.cn 2 A Vcc Vss B SCL SDA Marking side (top view) 1-16 PDF
Документация на BL24C16A-PARC 

DESCRIPTION

Дата модификации: 22.11.2016

Размер: 490.5 Кб

16 стр.

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    24AA02E48-I/SN (MCRCH)