CJ74LVC8T245BHN

JSCJ
JIANGSU CHANGJING ELECTRONICS TECHNOLOGY CO., LTD. 8-bit Dual Supply Translating Transceiver; 3-state CJ74LVC/LVCH8T245 Logic 1 Introduction 3 Features The CJ74LVC/LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable • Wide supply voltage range: - VCC(A): 1.2V to 5.5V - VCC(B): 1.2V to 5.5V • input (DIR), an output enable input (/OE) and dual Maxi...
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Корпус TSSOP-24
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JIANGSU CHANGJING ELECTRONICS TECHNOLOGY CO., LTD. 8-bit Dual Supply Translating Transceiver; 3-state CJ74LVC/LVCH8T245 Logic 1 Introduction 3 Features The CJ74LVC/LVCH8T245 are 8-bit dual supply translating transceivers with 3-state outputs that enable • Wide supply voltage range: - VCC(A): 1.2V to 5.5V - VCC(B): 1.2V to 5.5V • input (DIR), an output enable input (/OE) and dual Maximum data rates: - 420 Mbps (3.3V to 5.0V translation) supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2V and 5.5V - 210 Mbps (translate to 3.3V)) - 140 Mbps (translate to 2.5V) making the device suitable for translating between any of the low voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V - 75 Mbps (translate to 1.8V) - 60 Mbps (translate to 1.5V) bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control and 5.0V). Pins An, /OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR • Suspend mode • ±24mA output drive (VCC=3.0V) allows transmission from An to Bn and a LOW on DIR • Inputs accept voltages up to 5.5V allows transmission from Bn to An. The output enable input (/OE) can be used to disable the outputs so the • Low power consumption: 30uA maximum ICC • IOFF circuitry provides partial Power-down mode operation • Specified from -40°C to +125°C buses are effectively isolated. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current 4 Applications through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the CJ74LVCH8T245 holds unused or floating data inputs at a valid logic level. 2 Available Packages • Personal electronic • Industrial • Enterprise • Telecom DIR 2 22 PART NUMBER CJ74LVC8T245 CJ74LVCH8T245 PACKAGE TSSOP24 A1 OE 3 21 QFN5.5x3.5-24L B1 TSSOP24 QFN5.5x3.5-24L to other seven channels Note: For all available packages, please refer to the part Orderable Information. www.jscj-elec.com Logic diagram 1 Rev. – 1.0 PDF
Документация на CJ74LVC8T245BHN 

Дата модификации: 14.11.2025

Размер: 1.84 Мб

29 стр.

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