NCA9511-DSPR

NCA9511 Hot Swappable I2C Bus and SMBus Buffer Datasheet (EN) 1.2 Product Overview Applications The NCA9511 is a hot-swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock buses. Control circuitry prevents the backplane-side I2C lines (in) from being connected to the card-side I2C lines (out) until a stop command or bus idle ...
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Корпус SO-8 SOIC8
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NCA9511 Hot Swappable I2C Bus and SMBus Buffer Datasheet (EN) 1.2 Product Overview Applications The NCA9511 is a hot-swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock buses. Control circuitry prevents the backplane-side I2C lines (in) from being connected to the card-side I2C lines (out) until a stop command or bus idle condition occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances separated. During insertion, the SDA and SCL lines are pre-charged to 1 V to minimize the current required to charge the parasitic capacitance of the device.  Servers  Enterprise Switching  Telecom switching equipment  Base stations  Industrial automation equipment When the I2C bus is idle, the NCA9511 can be put into shutdown mode by setting the EN pin low, reducing power consumption. When EN is pulled high, the NCA9511 resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low. Functional Block Diagrams Device Information Part Number NCA9511-DMSR Package MSOP8 Body Size 3.00mm*3.00mm NCA9511-DSPR SOP8 4.90mm*3.90mm Key Features  Supports bidirectional data transfer of I2C bus signals  Operating power-supply voltage range of 2.7 V to 5.5 V  TA ambient air temperature range of -40 ℃ to 105 ℃  1-V pre-charge on all SDA and SCL lines prevents  corruption during live insertion  Accommodates standard mode and fast mode I2C devices  Supports clock stretching, arbitration and synchronization  Powered-off high-impedance I2C pins Figure 1. NCA9511 Block Diagram PDF
Документация на NCA9511-DMSR 

AD7792/AD7793 3-Channel, Low Noise, Low Power, 16/24-Bit ∑-Δ ADC with On-Chip In-Amp and Reference Data Sheet (Rev. A) Keywords:

Дата модификации: 05.05.2022

Размер: 2.9 Мб

20 стр.

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