NSI6602B-DSPNR

Novosense
NSi6602 High Reliability Isolated Dual-Channel Gate Driver Datasheet (EN) 1.5 Product Overview NSI6602 is a family of high reliability isolated dual-channel gate driver ICs which can be designed to drive power transistor up to 2MHz switching frequency. Each output could source 4A and sink 6A peak current with fast 25ns propagation delay and 5ns maximum delay matching. The NSI6602 provides 2500V...
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Корпус SOP-16
Напряжение изоляции RMS
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Кол-во приемников
Максимальная задержка сигнала
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NSi6602 High Reliability Isolated Dual-Channel Gate Driver Datasheet (EN) 1.5 Product Overview NSI6602 is a family of high reliability isolated dual-channel gate driver ICs which can be designed to drive power transistor up to 2MHz switching frequency. Each output could source 4A and sink 6A peak current with fast 25ns propagation delay and 5ns maximum delay matching. The NSI6602 provides 2500Vrms isolation per UL1577 in 5*5mm LGA13 package, 3000Vrms isolation in SOP16 (150mil) package, and 5700Vrms isolation in SOP16 (300mil) or SOP14 (300mil) package. System robustness is supported by 150kV/us typical common-mode transient immunity (CMTI). The driver operates with a maximum supply voltage of 25V, while the input-side accepts from 2.7V to 5V supply voltage. Under voltage lock-out (UVLO) protection is supported by all the power supply voltage pins. Safety Regulatory Approvals  UL recognition: ◼ LGA13: 2500Vrms for 1 minute per UL1577 ◼ SOP16/SOP14(300mil): 5700Vrms for 1 minute per UL1577 ◼ SOP16(150mil): 3000Vrms for 1 minute per UL1577  DIN VDE V 0884-11:2017-01  CSA component notice 5A Key Features  Isolated dual channel driver  CQC certification per GB4943.1-2011 Applications  Input side supply voltage: 2.7V to 5.5V  Isolated DC-DC and AC-to-DC power supplies in server, telecom, and industry  Driver side supply voltage: up to 25V with UVLO  DC-to-AC solar inverters  4A peak source and 6A peak sink output  Motor drives and EV charging  High CMTI: ±150kV/us typical  UPS and battery chargers  25ns typical propagation delay Functional Block Diagram  5ns maximum delay matching  Programmable deadtime VDDI INA DT  Accepts minimum input pulse width 20ns  Operation temperature: -40℃~125℃ VDDA DIS INB MOD DEMOD UVLO OUTA GNDA UVLO, Disable & DeadTime Isolation barrier  6ns maximum pulse width distortion Functional Isolation VDDB MOD DEMOD UVLO GNDI OUTB GNDB Figure 0.1 NSI6602 Block Diagram Copyright © 2021, NOVOSENSE Page 1 PDF
Документация на NSI6602A-DLAR 

Дата модификации: 11.11.2021

Размер: 1.53 Мб

31 стр.

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