RS1473XTQC16

Runic
RS1473 14-Bit, 2 MSPS, Dual-Channel, Single-Ended Analog-to-Digital Converters 1 FEATURES 3 DESCRIPTIONS • Sample Rate: 2 MSPS The RS1473 is a 14-bit, 2MSPS analog-to-digital • INL 2.5 LSB (MAX) converter (ADC) that offers Single-Ended inputs. The • Wide Supply Range: device operates at a 2MSPS sample rate with a standard Analog: 2.7 V to 5.25 V 16 clock data frame. The device incl...
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Корпус QFN163X3
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RS1473 14-Bit, 2 MSPS, Dual-Channel, Single-Ended Analog-to-Digital Converters 1 FEATURES 3 DESCRIPTIONS • Sample Rate: 2 MSPS The RS1473 is a 14-bit, 2MSPS analog-to-digital • INL 2.5 LSB (MAX) converter (ADC) that offers Single-Ended inputs. The • Wide Supply Range: device operates at a 2MSPS sample rate with a standard Analog: 2.7 V to 5.25 V 16 clock data frame. The device includes a two-channel Digital: 1.65 V to AVDD input multiplexer and a low-power successive • 14-Bit No Missing Code Resolution approximation register (SAR) ADC with an inherent • Auto Power-Down at Lower Speeds sample-and-hold (S/H) input stage. • Two Single-Ended Inputs • Operating Temperature Range -40 °C to The RS1473 supports a wide analog supply range that 125 °C allows the full-scale input range to extend to 5 V single- • SPI-Compatible Interface ended. A simple SPI, with a digital supply that can • Package: QFN3x3-16 operate as low as 1.65 V, allows for easy interfacing to a wide variety of digital controllers. Automatic powerdown can be enabled when operating at slower speeds 2 APPLICATIONS to dramatically reduce power consumption. • Optical networking • Sensors Measurements • Portable Instrumentation The RS1473 is offered in a leadless QFN3x3-16 package • Medical Instrumentation and is specified over a temperature range of -40°C to • Data Acquisition Systems +125°C. • Battery-Powered Equipment Device Information (1) PART NUMBER PACKAGE BODY SIZE(NOM) RS1473 QFN3x3-16 3.00mm x 3.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. AVDD REF REFGND DVD D RS1473 AIN0 AIN0GND MUX SAR ADC S/H PDEN CS SPI SCLK SDO AIN1GND AIN1 CH_SEL GND Figure 1. Block Diagram REV A.1 1 / 28 www.run-ic.com PDF
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Дата модификации: 01.02.2024

Размер: 1.38 Мб

28 стр.

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