Серия микросхем памяти P24C512B

Общие характеристики

	Раздел	Память
	Тип памяти
	Подтип памяти
	Интерфейс
	Объём памяти
	Организация памяти
	Напряжение питания

Документация на серию P24C512B

P24C512B I2C-Compatible Serial E2PROM Data Sheet Rev. 1.4 General Description 2 The P24C512B is a 512-Kbit I C-compatible Serial EEPROM (Electrically Erasable Programmable Memory) device. It contains a memory array of 64 K × 8 bits, which is organized in 128-byte per page. P24C512B provides the following devices for different application. Device Selection Table Device Name Voltage Range Temp. Range Max. Clock Frequency P24C512B -MI 1.7V~5.5V -40°C ~ 85°C 1MHz P24C512B -NK 1.8V~5.5V -40°C~105°C 1MHz P24C512B -DE 2.5V~5.5V -40°C~125°C [1] [1] 1MHz Note 1: 400 kHz for VCC < 2.5V. Features   Single Supply Voltage and High Speed  Minimum operating voltage down to 1.7V  1 MHz clock from 2.5V to 5.5V  400kHz clock from 1.7V to 2.5V Low power CMOS technology  Read current 500uA, maximum  Write current 2.5mA, maximum  Schmitt Trigger, Filtered Inputs for Noise Suppression  Sequential & Random Read Features  128 byte Page Write Modes, Partial Page Writes Allowed    Write protect of the whole memory array Additional Write Lockable Page Self-timed Write Cycle (5ms maximum)  High Reliability   Endurance: 1 Million Write Cycles  Data Retention: 100 Years  HBM: 6KV  Latch up Capability: +/- 200mA Package: PDIP, SOP, TSSOP, and DFN/UDFN 1/21

Документация на серию P24C512B

Features

Дата модификации: 12.03.2022

Размер: 690.9 Кб

21 стр.

найти P24C512B.pdf

Товары серии P24C512B

Наименование	i	Упаковка	T раб	Корпус
P24C512B-D8H-MIR (PUYA)				—
P24C512B-SSH-MIR (PUYA)		в ленте 4000 шт		SOP-8
P24C512B-SSH-MIT (PUYA)		в линейках 100 шт		SOP-8
P24C512B-TSH-MIR (PUYA)		в ленте 4000 шт		TSSOP-8
P24C512B-TSH-MIT (PUYA)				TSSOP-8
P24C512B-TSH-MKR (PUYA)				TSSOP-8
P24C512B-TSH-MKT (PUYA)				TSSOP-8
P24C512B-UNH-MIR (PUYA)		3000 шт		DFN-8 UDFN8